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1 * this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 9.30.1997 general description the em78247b/447b is an 8-bit microprocessor with low-power, high speed cmos technology. integrated onto a single chip are on-chip watchdog timer (wdt), ram, rom, programmable real time clock/ counter, power down mode and bi-directional tri-state i/o ports. it can be developed as cordless phone or other applications. features ? operating voltage range : 2.5v ~ 5.5v ? available in temperature range: 0 c ~ 70 c. ? operating frequency range : crystal type : dc ~ 20mhz at 5v dc ~ 8mhz at 3v rc type : dc ~ 4mhz at 5v dc ~ 4mhz at 3v ? 2k x 13 on chip rom (em78247b), or ? 4k x 13 on chip rom (em78247b) ? 9 special function registers ? 148 8 general purpose registers (sram). ? 3 bi-directional tri-state i/o ports (24 i/o pins) ? 5 level stack for subroutine nesting ? 8-bit real time clock/counter (tcc) with selective signal sources and trigger edges, and with overflow interrupt ? selectable oscillator options: xtal1 type (high frequency) xtal2 type (32.768khz) rc type external clock input ? two oscillator periods per instruction cycle ? power down mode ? programmable wake up from sleep circuit on i/o ports ? programmable free running on-chip watchdog timer ? ten pull-up and wake-up pins ? two open-drain pins ? two r-option pins ? interrupt function available ? 32 pin dip, soic em78247b/447b patent number : 61007 (r.o.c) patent pending : 83216083 (r.o.c) 8-bit micro-controller for general purpose product
* this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 2 9.30.1997 pin assignments p55 p54 tcc v dd nc v ss int p50 p51 p52 p53 p60 p61 p62 p63 p64 p56 p57 reset osci osco p77 p76 p75 p74 p73 p72 p71 p70 p67 p66 p65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 em78247b/447b dip,soic functional block diagram p50~p57
3 * this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 9.30.1997 pin descriptions symbol i/o function osci i xtal type : crystal input terminal or external clock input pin. rc type : rc oscillator input pin. osco i/o xtal type : output terminal for crystal oscillator or external clock input pin. rc type : clock output with a period of one instruction cycle is put on this pin. tcc i real time clock/counter, schmitt trigger input pin. must be tied to v dd or v ss if not in use. reset i schmitt trigger input pin. if this pin remains logic low, the controller is reset. p70~p77 i/o port 7 is an 8-bit bi-directional i/o port. p74 and p75 can be pulled-high internally by software control. p76 and p77 can have open-drain output by software control. p70 and p71 are also the r-option pins. p60~p67 i/o port 6 is an 8-bit bi-directional i/o port. they can be pulled-high internally by software control. p50~p57 i/o port 5 is an 8-bit bi-directional i/o port. int i falling edge schmitt triggered interrupt input pin. it indicates an interrupt if interrupt is enabled. internal pull-up resistor 50k w . nc - no connection. v dd - power supply pin. v ss - ground pin. function descriptions operational registers r0 (indirect addressing register) ? r0 is not a physically implemented register. it is useful as indirect addressing pointer. any instruction using r0 as register actually accesses data pointed by the ram select register (r4). r1 (tcc) ? increased by an external signal edge applied to tcc pin, or by the instruction cycle clock. ? written and read by the program as any other register. r2 (program counter) & stack ? depending on the device type, r2 and hardware stack are 11/12 bits wide. the structure is depicted in fig. 3. ? generates 2k/4k 13 on-chip rom addresses to the relative programming instruction codes. one program page is 1k words long. ? r2 is set all 1s upon a reset condition. ? jmp instruction allows the direct loading of the lower 10 program counter bits. thus, jmp allows jump to any location on one page.
* this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 4 9.30.1997 ? call instruction loads the lower 10 bits of the pc, and then pc+1 is pushed into the stack. thus, the subroutine entry address can be any location on one page. ? ret (retl k, reti) instruction loads the program counter with the contents at the top of stack. ? mov r2,a allows the loading of an address from the a register to the lower 8 bits of pc, and the ninth and tenth bits (a8~a9) of pc are cleared. ? add r2,a allows a relative address be added to the current pc, and the ninth and tenth bits of pc are cleared. ? any instruction which writes to r2 (e.g. add r2,a, mov r2,a, bc r2,6, ) (except tbl) will cause the ninth and tenth bits (a8~a9) of pc to be cleared. thus, the computed jump is limited to the first 256 locations of any program page. ? tbl allows a relative address be added to the current pc (r2+a ? r2), and contents of the ninth and tenth bits (a8~a9) of pc are not changed. thus, the computed jump can be on the second (or third, 4th) 256 locations on one program page. ? in case of em78247b, the most significant bit (a10) will be loaded with the content of bit ps0 in the status register (r3) upon the execution of a jmp, call, or any instruction which writes to r2. ? in case of EM78447B, the most significant bits (a10~a11) will be loaded with the contents of bits ps0~ps1 in the status register (r3) upon the execution of a jmp, call, or any instruction which writes to r2. fig. 3 program counter organization em78447a em78447a em78247a/447a EM78447B em78247b em78247b/447b EM78447B
5 * this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 9.30.1997 r3 (status register) 7 6 543210 gp ps1 ps0 t p z dc c bit 0 (c) carry flag bit 1 (dc) auxiliary carry flag bit 2 (z) zero flag. set to 1 if the result of an arithmetic or logic operation is zero. bit 3 (p) power down bit. set to 1 during power on or by a wdtc command and reset to 0 by a slep command. bit 4 (t) time-out bit. set to 1 by the slep and wdtc command, or during power up and reset to 0 by wdt timeout. bit 5 (ps0) page select bits. ps0~ps1 are used to preselect a program memory page. when executing ~6 (ps1) a jmp, call, or other instruction which causes the program counter to be changed (e.g. mov r2,a), ps0~ps1 are loaded into the 11th and 12th bits of the program counter, selecting one of the available program memory pages. note that ret (retl, reti) instruction does not change the ps0~ps1 bits. that is, the return will be always to the page from where the subroutine was called, regardless of the current setting of ps0~ps1 bits. ps1 bit is not used (read as 0) and cannot be modified in em78247b. ps1 ps0 program memory page (address) 0 0 page 0 (000-3ff) (em78247b/447b) 0 1 page 1 (400-7ff) (em78247b/447b) 1 0 page 2 (800-bff) (EM78447B) 1 1 page 3 (c00-fff) (EM78447B) bit 7 (gp) general read/write bit. r4 (ram select register) ? bits 0~5 are used to select the registers (address: 00~3f) in the indirect addressing mode. ? bits 6~7 determine which bank is activated among the 4 banks. ? see the configuration of the data memory in fig. 4. r5~r7 (port 5 ~ port 7) ? three 8-bit i/o registers.
* this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 6 9.30.1997 fig. 4 data memory configuration r8 ~ r1f, r20~r3e (general purpose register) ? r8~r1f and r20~r3e (including banks 0~3) are general purpose registers. r3f (interrupt status register) 7 6 5 4 32 10 - - - - exif - - tcif ? bit 0 (tcif) tcc timer overflow interrupt flag. set when tcc timer overflows, reset in software. ? bit 3 (exif) external interrupt flag. set by falling edge on /int pin, reset in software. ? bits 1~2, 4~7 not used. ? 1 means interrupt request, 0 means non-interrupt 20
7 * this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 9.30.1997 ? r3f can be cleared by instruction and cannot be set by instruction. ? iocf is the interrupt mask register. ? note that reading r3f by instruction will get the result of logic and of r3f and iocf. special purpose registers a (accumulator) ? internal data transfer, or instruction operand holding ? its not an addressable register. cont (control register) 76 5 43210 phen int ts te pab psr2 psr1 psr0 bit 0 (psr0)~bit 2 (psr2) tcc/wdt prescaler bits. psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 bit 3 (pab) prescaler assignment bit. 0: tcc 1: wdt bit 4 (te) tcc signal edge 0: increment from low to high transition on tcc pin 1: increment from high to low transition on tcc pin bit 5 (ts) tcc signal source 0: internal instruction cycle clock 1: transition on tcc pin bit 6 (int) interrupt enable flag which cannot be written by contw instruction. 0: interrupt masked by disi or hardware interrupt. 1 : interrupt enabled by eni/reti instruction. bit 7 (phen) i/o pin pull-high enable flag 0: p60~p67 and p74~p75 have internal pull-high. 1: pull-high is disabled. ? bits 0~5, 7 of cont register are readable and writable. ioc5 ~ ioc7 (i/o port control register) ? 1 put the relative i/o pin into high impedance, while 0 put the relative i/o pin as output. ? ioc5 ~ ioc7 are three i/o direction control registers.
* this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 8 9.30.1997 ioce (wdt control register) 76543210 - ode wte slpc roc - - wue bit 0 (wue) control bit used to enable wake-up function of p60~p67, p74~p75. 0: enable wake-up function 1: disable wake-up function wue bit is readable and writable. bit 3 (roc) roc is used for the r-option. setting roc to 1 will enable the status of r-option pin (p70, p71) to be read by the controller. clearing roc will disable the r-option function. if the r-option function is used, the user must connect the p71 pin or/and p70 pin to vss by a 560k external resistor (rex). if rex is connected/disconnected, the status of p70(p71) will be read as 0/1 when roc is set to 1. refer to fig. 7(b). roc bit is readable and writable. bit 4 (slpc) this bit is set by hardware at the falling edge of wake-up signal and is cleared by software. slpc is used to control the operation of oscillator. the oscillator is disabled (oscillator is stopped, the controller enters the sleep2 mode) on high-to-low transition on slpc bit and is enabled (the controller is awakened from sleep2 mode) on low-to-high transition on slpc bit. in order to ensure the stable output of the oscillator, once the oscillator is disabled and is enabled again, there is a delay for approximately 18 ms (oscillator start-up timer, ost) before the next instruction of program being executed. the ost is always activated by wake- up from sleep mode whether the code option bit wtc is 0 or not. after waking up, the wdt is enabled if code option wtc is 1. the block diagram of sleep2 mode and wake-up caused by input triggered is depicted in fig. 5. bit 5 (wte) control bit used to enable watchdog timer. wte bit is used only if the code option bit wtc is 1. if wtc bit is 1, then wdt is disabled/enabled by wte bit. 0: disable wdt 1: enable wdt wte bit is not used if the code option bit wtc is 0. that is, if wtc bit is 0, wdt is always disabled no matter what the wte bit is. wte bit is readable and writable. bit 6 (ode) open-drain control bit. 0: both p76 and p77 are normal i/o pins. 1: both p76 and p77 pins have open-drain output. ode bit is readable and writable. bits 1,2,7 not used.
9 * this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 9.30.1997 fig. 5 block diagram of sleep mode and wake-up circuits on i/o ports iocf (interrupt mask register) 76543210 - - - - exie - - tcie bit 0(tcie) tcif interrupt enable bit. 0: disable tcif interrupt. 1: enable tcif interrupt. bit 3 (exie) exif interrupt enable bit. 0: disable exif interrupt. 1: enable exif interrupt. bits 1~2,4~7 not used. ? individual interrupt is enabled by setting its associated control bit in iocf to 1. ? global interrupt is enabled by eni instruction and is disabled by disi instruction. refer to fig. 9. ? iocf register is readable and writable. tcc/wdt prescaler
* this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 10 9.30.1997 there is an 8-bit counter available as prescaler for the tcc or wdt. the prescaler is available for the tcc only or wdt only at the same time and the pab bit of cont register is used to determine the prescaler assignment. the psr0~psr2 bits determine the prescale ratio. the prescaler will be cleared by instructions which write to tcc each time, when assigned to tcc mode. the wdt and prescaler, when assigned to wdt mode, will be cleared by the wdtc and slep instructions. fig. 6 depicts the circuit diagram of tcc/wdt. ? r1(tcc) is an 8-bit timer/counter. the clock source of tcc can be internal clock or external clock input (edge selectable from tcc pin). if tcc signal source is from internal clock, tcc will increase by one in every instruction cycle (without prescaler). if tcc signal source is from external clock input, tcc will increase by 1 on every falling edge or rising edge of tcc pin. ? the watchdog timer is a free running on-chip rc oscillator. the wdt will keep running even the oscillator driver has been turned off (i.e. in sleep mode). during the normal operation or the sleep mode, a wdt time- out (if enabled) will cause the device to reset. the wdt can be enabled or disabled at any time during the normal mode by software programming (if code option bit wtc is 1). refer to wte bit of ioce register. with no presacler, the wdt time-out period is approximately 18 ms. i/o ports the i/o registers, port 5 ~ port 7, are bi-directional tri-state i/o ports. p60~p67, p74~p75 can have internal pull-high and wake-up function by software control. p76~p77 can have open-drain output by software control. p70~p71 are the r-option pins which are enabled by software. while r-option function is used, p70~p71 are recommended to be used as output pins. during the period of r-option being enabled, p70~p71 must be programmed as input pins. if external resistor is connected to p70(p71) for r-option function, the current consumption should be noticed in the applications that low power are concerned. the i/o ports can be defined as input or output pins by the i/o control registers (ioc5~ioc7) under program control. the i/o registers and i/o control registers are both readable and writable. the i/o interface circuit is shown in fig. 7. note that the source is different between the reading path of input and output pin while reading the i/o port. fig. 6 block diagram of tcc and wdt
11 * this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 9.30.1997 fig. 7(a) the circuit of i/o port and i/o control register fig. 7(b) the circuit of i/o port with r-option (p70,p71)
* this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 12 9.30.1997 fig. 8 the block diagram of reset of controller reset and wake-up the reset can be caused by (1) power on reset (2) reset pin input low, or (3) wdt timeout. (if enabled) the device will be kept in a reset condition for a period of approx. 18ms (one oscillator start-up timer period) after the reset is detected. once th reset occurs, the following functions are performed. ? the oscillator is running, or will be started. ? the program counter (r2) is set to all 1. ? when power on, bits 5~6 of r3 and the upper 2 bits of r4 are cleared. ? all i/o port pins are configured as input mode (high-impedance state). ? the watchdog timer and prescaler are cleared. ? the watchdog timer is enabled if code option bit wtc is 1. ? the cont register is set to all 1 except bit 6 (int flag). ? bits 3,6 of ioce register is cleared, bits 0,4~5 of ioce register are set to 1 ? bits 0,3 of r3f and bits 0,3 of iocf registers are cleared. the sleep mode (power down mode) can be entered by executing the slep instruction (named as sleep1 mode). while entering sleep mode, the wdt (if enabled) is cleared but keeping running. the controller can be awakened by (1) wdt timeout (if enabled), or (2) external reset input on /reset pin. the two cases will cause the controller to be reset. the t and p flags of r3 can be used to determine the source of the reset (wake-up). in addition to the basic sleep1 mode, em78247b/447b has another sleep mode (caused by clearing slpc bit of ioce register, named as sleep2 mode). in the sleep2 mode, the controller can be awakened by
13 * this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 9.30.1997 (a) input triggered, refer to fig. 5. when wake-up, the controller will continue to execute program in-line. in this case, before entering sleep2 mode, the wake-up function of the trigger sources (p60~p67, and p74~p75) should be selected (e.g. input pin) and enabled (e.g. pull-high, wake-up control). one caution should be noted is that after waking up, the wdt is enabled if code option bit wtc is 1. the wdt operation (to be enabled or disabled) should be appropriately controlled by software after waking up. (b) wdt time-out (if enabled) or external reset input on /reset pin. when wake-up, will cause the controller reset. interrupt the em78247b/447b has the following interrupts: (1) tcc overflow interrupt (2) external interrupt (/int). r3f is the interrupt status register which records the interrupt request in flag bit. iocf is the interrupt mask register. global interrupt is enabled by eni instruction and is disabled by disi instruction. when one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 001h. once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the r3f register. the interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. the flag in the interrupt status register (r3f) is set regardless of the status of its mask bit or the execution of eni instruction. note that reading r3f will get the output of logic and of r3f and iocf. refer to fig. 9. the reti instruction exits interrupt routine and enables the global interrupt (execution of eni instruction). when an interrupt is generated by int instruction (when enabled), causes the next instruction to be fetched from address 002h. fig. 9 interrupt input circuit
* this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 14 9.30.1997 instruction status binary hex hnemonic operation affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a ? cont none 0 0000 0000 0011 0003 slep 0 ? wdt, stop oscillator t,p 0 0000 0000 0100 0004 wdtc 0 ? wdt t,p 0 0000 0000 rrrr 000r iow r a ? iocr none 0 0000 0001 0000 0010 eni enable interrupt none 0 0000 0001 0001 0011 disi disable interrupt none 0 0000 0001 0010 0012 ret [top of stack] ? pc none 0 0000 0001 0011 0013 reti [top of stack] ? pc, enable interrupt none 0 0000 0001 0100 0014 contr cont ? a none 0 0000 0001 rrrr 001r ior r iocr ? a none 0 0000 0010 0000 0020 tbl r2+a ? r2, bits 8~9 of r2 unchanged z,c,dc 0 0000 01rr rrrr 00rr mov r,a a ? r none 0 0000 1000 0000 0080 clra 0 ? az 0 0000 11rr rrrr 00rr clr r 0 ? rz 0 0001 00rr rrrr 01rr sub a,r r-a ? a z,c,dc 0 0001 01rr rrrr 01rr sub r,a r-a ? r z,c,dc 0 0001 10rr rrrr 01rr deca r r-1 ? az 0 0001 11rr rrrr 01rr dec r r-1 ? rz 0 0010 00rr rrrr 02rr or a,r a r ? az 0 0010 01rr rrrr 02rr or r,a a r ? rz 0 0010 10rr rrrr 02rr and a,r a & r ? az 0 0010 11rr rrrr 02rr and r,a a & r ? r z 0 0011 00rr rrrr 03rr xor a,r a ? r ? a z 0 0011 01rr rrrr 03rr xor r,a a ? r ? r z 0 0011 10rr rrrr 03rr add a,r a + r ? a z,c,dc instruction set each instruction in the instruction set is a 13-bit word divided into an op code and one or more operands. all instructions are executed within one single instruction cycle (consists of 2 oscillator periods), unless the program counter is changed by (a) executing the instruction mov r2,a, add r2,a, tbl, or any instruction which writes to r2 (e.g. sub r2,a, bs r2,6, clr r2, ). (b) call, ret, reti, retl, jmp, conditional skip (jbs, jbc, jz, jza, djz, djza) tested to be true. in these cases, the execution takes two instruction cycles. in addition, the instruction set has the following features: (1). every bit of any register can be set, cleared, or tested directly. (2). the i/o register can be regarded as general register. that is, the same instruction can operates on i/o register. the symbol r represents a register designator which specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. bits 6 and 7 in r4 determine the selected register bank. b represents a bit field designator which selects the number of the bit, located in the register r, affected by the operation. k represents an 8 or 10-bit constant or literal value.
15 * this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 9.30.1997 instruction status binary hex hnemonic operation affected 0 0011 11rr rrrr 03rr add r,a a + r ? r z,c,dc 0 0100 00rr rrrr 04rr mov a,r r ? a z 0 0100 01rr rrrr 04rr mov r,r r ? r z 0 0100 10rr rrrr 04rr coma r /r ? a z 0 0100 11rr rrrr 04rr com r /r ? r z 0 0101 00rr rrrr 05rr inca r r+1 ? a z 0 0101 01rr rrrr 05rr inc r r+1 ? rz 0 0101 10rr rrrr 05rr djza r r-1 ? a, skip if zero none 0 0101 11rr rrrr 05rr djz r r-1 ? r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) ? a(n-1), r(0) ? c, c ? a(7) c 0 0110 01rr rrrr 06rr rrc r r(n) ? r(n-1), r(0) ? c, c ? r(7) c 0 0110 10rr rrrr 06rr rlca r r(n) ? a(n+1), r(7) ? c, c ? a(0) c 0 0110 11rr rrrr 06rr rlc r r(n) ? r(n+1), r(7) ? c, c ? r(0) c 0 0111 00rr rrrr 07rr swapa r r(0-3) ? a(4-7), r(4-7) ? a(0-3) none 0 0111 01rr rrrr 07rr swap r r(0-3) ? r(4-7) none 0 0111 10rr rrrr 07rr jza r r+1 ? a, skip if zero none 0 0111 11rr rrrr 07rr jz r r+1 ? r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 ? r(b) none 0 101b bbrr rrrr 0xxx bs r,b 1 ? r(b) none 0 110b bbrr rrrr 0xxx jbc r,b if r(b)=0, skip none 0 111b bbrr rrrr 0xxx jbs r,b if r(b)=1, skip none 1 00kk kkkk kkkk 1kkk call k pc+1 ? [sp], (page, k) ? pc none 1 01kk kkkk kkkk 1kkk jmp k (page, k) ? pc none 1 1000 kkkk kkkk 18kk mov a,k k ? a none 1 1001 kkkk kkkk 19kk or a,k a k ? az 1 1010 kkkk kkkk 1akk and a,k a & k ? az 1 1011 kkkk kkkk 1bkk xor a,k a ? k ? az 1 1100 kkkk kkkk 1ckk retl k k ? a, [top of stack] ? pc none 1 1101 kkkk kkkk 1dkk sub a,k k-a ? a z,c,dc 1 1110 0000 0010 1e02 int pc+1 ? [sp], 002h ? pc none 1 1111 kkkk kkkk 1fkk add a,k k+a ? a z,c,dc this instruction can operate on ioc5~ioc7, ioce~iocf only. this instruction is not recommended to operate on r3f. this instruction cannot operate on r3f.
* this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 16 9.30.1997 code option register the em78247b/447b has one code option register which is not part of the normal program memory. the option bits cannot be accessed during normal program execution. 765432 10 - - - ck2 - wtc hlf ms bit 0 (ms): oscillator type selection. 0: rc type 1: xtal type (xtal1 and xtal2) bit 1 (hlf): xtal frequency selection. 0: xtal2 type (low frequency, 32.768khz) 1: xtal1 type (high frequency) this bit is useful only when bit 0 (ms) is 1. when ms is 0, hlf must be 0. bit 2 (wtc): wdt option. 0: wdt is always disabled. control bit wte in ioce is unused. 1: wdt is enabled. wdt can be disabled/enabled by software programming. control bit wte in ioce register is used to disable/enable wdt. bit 3 (typ): allways 0 for em78247b/447b. bit 4 (ck2): input clock divided by two selection. 0: system clock is from oscillator clock directly. 1: system clock is from oscillator clock divided by two. bits 5~7: not used, must be 0s.
17 * this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 9.30.1997 absolute maximum ratings items sym. condition rating temperature under bias t opr 0 c to 70 c storage temperature t str -65 c to 150 c input voltage v in -0.3v to +6.0v output voltage v o -0.3v to +6.0v dc electrical characteristic (t a =0 c ~ 70 c, v dd =5.0v, v ss =0v) parameter sym. condition min. typ. max. unit input leakage current i il1 v in = v dd , v ss 1 m a for input pins input high voltage v ih 2.0 v input low voltage v il 0.8 v input high threshold voltage v iht reset, tcc,int 0.85v dd v dd v input low threshold voltage v ilt reset, tcc,int v ss 0.15v dd v clock input high voltage v ihx osci 3.5 v clock input low voltage v ilx osci 1.5 v output high voltage v oh1 i oh = -12.0ma 2.4 v (port 5,6,7) output low voltage v ol1 i ol = 12.0ma 0.4 v (port 5,6) output low voltage v ol2 i ol = 20.0ma 0.4 v (port 7 only) pull-high current i ph pull-high active, input pin at v ss -50 -100 -240 m a power down current i sb all input and i/o pins at v dd , output 10 m a pin floating, wdt enabled operating supply current i cc1 reset='high', fosc=4mhz (ms="1", hlf="1",ck2="0"), output pin floating 2 ma operating supply current i cc2 reset='high', fosc=10mhz (ms="1", hlf="1",ck2="0"), output pin floating 5 ma operating supply current i cc3 reset='high', fosc=32.768khz (v dd =3.25v) (ms="1", hlf="0",ck2="0"), output pin floating, wdt disabled 30 m a * n= selected prescaler ratio. ac electrical characteristics (t a =0 c ~ 70 c, v dd =5.0v, v ss =0v) input clk duty cycle dclk 45 50 55 % instruction cycle time tins xtal type 100 dc ns (ck2="0") rc type 500 dc ns tcc input period ttcc (tins+20)/n* ns watchdog timer period twdt ta = 25 c18ms device reset hold period tdrh ta = 25 c18ms parameter symbol condition min. typ. max. unit
* this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 18 9.30.1997
19 * this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 9.30.1997 pad no. symbol x y 1 p55 -120.4 1035.2 2 p54 -317.7 1035.2 nc -520.1 1024.8 3 tcc -747.6 1032.7 4 vdd -935.0 1032.7 nc -897.2 835.8 5nc 6 gnd -927.1 540.5 7 int -937.5 343.3 8 p50 -937.5 143.2 9 p51 -937.5 -54.1 10 p52 -937.5 -251.4 11 p53 -937.5 -448.7 12 p60 -909.9 -1057.5 13 p61 -712.6 -1057.5 14 p62 -515.3 -1057.5 15 p63 -318.0 -1057.5 16 p64 -120.7 -1057.5 nc 54.4 -1057.5 17 p65 229.5 -1057.5 18 p66 426.8 -1057.5 19 p67 624.1 -1057.5 20 p70 832.9 -1057.5 21 p71 920.2 -774.8 pad diagram chip size : 2200 m m x 2440 m m 4 3 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 2 reset osci p57 p56 p55 p54 nc tcc vdd nc gnd int p50 p51 p52 p53 p60 p61 p62 p63 p64 nc p65 p66 p67 p70 p71 p72 p73 p74 p75 p76 p77 osco (0,0) em78247/447b 32
* this specification are subject to be changed without notice. em78247b/447b 8-bit micro-controller for general purpose product 20 9.30.1997 unit : m m note : for pcb layout, ic substrate must be floated, or connect to v ss . pad no. symbol x y 22 p72 920.2 -564.1 23 p73 920.2 -324.6 24 p74 920.2 -125.4 25 p75 920.2 114.1 26 p76 920.2 313.3 27 p77 920.2 552.8 28 osco 906.9 1035.2 29 osci 671.3 1035.2 30 reset 473.8 1032.7 31 p57 274.2 1035.2 32 p56 76.9 1035.2

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